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ABSTRACT

A SYSTEM INVOLVING THE USE OF FAULT SIMULATION FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVEL ELECTRICAL SIGNAL TEST PATTERN FOR A NON-LINEAR INTEGRATED CIRCUIT. FIRST, FOR EACH &#34;STUCK&#34; FAULT TO BE DETECTED BY THE REDUCED PATTERN, THE NUMBER OF THE PATTERN INCREMENT ON WHICH SAID FAULT IS DETECTED IN THE ORIGINAL PATTERN IS DETERMINED. THEN, FOR EACH STUCK FALT, THE PATTERN INCREMENT ON WHICH THE FAULT WAS DETECTED IN THE ORIGINAL TEST PATTERN IS APPLIED TO A &#34;GOOD&#34; CIRCUIT COMPUTER SIMULATION AND A &#34;BAD&#34; CIRCUIT COMPUTER SIMULATION REPRESENTATIVE OF SAID FAULT. IF THERE IS A &#34;FAIL TO COMPARE,&#34; THE APPLIED PATTERN ALONE IS SUFFICIENT TO DETECT THE FAULT. HOWEVER, IF THE OUTPUTS FROM BOTH SIMULATIONS COMPARE, AN INCREMENT SEQUENCE CONSISTING OF THE INCREMENT NEXT PRECEDING THE PRE-   VIOUSLY APPLIED INCREMENT FOLLOWED BY THE APPLIED INCREMENT IS REAPPLIED TO THE GOOD AND BAD SIMULATIONS, AND THE PROCEDURE IS REPEATED, EACH TIME ADDING THE NEXT PRECEDING INCREMENT TO THE SEQUENCE UNTIL A FAIL TO COMPARE   IS ACHIEVED. SUCH A SEQUENCE IS DETERMINED FOR EACH STUCK FAULT.

DEFENSIVE PUBLICATION UNITED STATES PATENT OFFICE Published at the request of the applicant or owner in accordance with the Notice of Dec. 16, 1969, 869 O.G. 687. The abstracts of Defensive Publication applications are identified by distinctly numbered series and are arranged chronologically. The heading of each abstract indicates the number of pages of specification, including claims and sheets of drawings contained in the application as Originally filed. The files of these applications are available to the public for inspection and reproduction may be purchased for 30 cents a sheet.

Defensive Publication applications have not been examined as to the merits of alleged invention. The Patent Office makes no assertion as to the novelty of the disclosed subject matter.

PUBLISHED NOVEMBER 5, 1974:

Int. Cl. G06f 11/00 US. Cl. 235151.3 5 Sheets Drawing. 21 Pages Specification TEST PATTERN WITH A PLURALITY OF 20/ INCREIIENTS, EACN WITII A PLURALITY 0F PARALLEL. BILEVEL SICNALS LIST OF ALL STUCK FAULTS AT CIRCUIT POINTS TO BE TESTED APPLY NEXT SUCCEEUING PATTERN INCREI IEIIT TO INPUTS OF "GOOD" CIRCUIT 25 AND EACN REMAINING "BIIO" CIRCUIT COMPARE OUTPUT 0F "OUUD CIRCUIT INITII EACH 0F OUTPUTS CF "IIAO' CIRCUITS DO ANY OE'BAD' CIRCUITS FAIL TO COMPARE WITH "BOOD' STORE CIRCUIT FAULT 23/ OF 'IlAO" CIRCUIT AND PATTERN INCREIIENT NO.

STUP APPLYING TEST 29 PATTERN T0 "FAIL TO COIIPARE" CIRCUIT AUI] ONE TO INCRENEIIT COUNTER A system involving the use of fault simulation for reducing the number of increments in a bilevel electrical signal test pattern for a non-linear integrated circuit. First, for each stuck fault to be detected by the reduced PUBLISHED NOVEMBER 5, 1974 TROII TIC-i FAULT LIST OF EACH EAULT' UETECTED 32 AND PATTERN INCREMENT NO. DETECTING SAID FAULT LOAD rn INTO FAULT COUNTER; m NUHBER (IF FAULTS mu *n mm" mcmzur I0 34 "noun" cmcunx to "m" cmcun CORRESPONDING T0 FAULT DETECTED n sun murmur O '6 DO" I 'BAO" FAIL TO COMPARE STORE SEDUENCE i TNRDUCII n INCRENENTS, AS NECESSARY TO TEST FOR FAULT BEING EXAIIINEO APPLY PATTERN IHCRENENT SEOUENCE *1 THROUGH n TO SAID "RAD" A "COOL!" CIRCUITS BRANCH FOR NEXT FAULT, "I3 DETERIIINE n FROM LIST *i.= NUMBER IN INCREIIENT COUNTER *n=TNE NEXT HIGHEST PATTERN INCREIIENT EDIT A FAULT REHAINING ON THE FAULT LIST SEUUENCE (.L-n) NECESSARY TO OETECT EACH FAULT viously applied increment followed by the applied increment is reapplied to the good and bad simulations, and the procedure is repeated, each time adding the next preceding increment to the sequence until a fail to compare IRON FIG. IA

LATIDN 0F 'GUDD' A "BAD" CIRCUITS SIMU ALL APPLY SEQUENCE (l-n) TO 'GOOD' It TO "DAD" CIRCUITS CORRESPONDING SA TD FAULTS REMAINING 0N FAULT LIST DD ANY ADDITIONAL "BAD" CIRCUITS FAIL TO COMPARE ADD THE ADDITIONAL FAULTS T0 5 THE STORED EAULTS WHICH SEDUENCE (.L-n) DETECTS REMOVE ADDITIONAL FAULTS FROM FAULT LIST TD TIC. IA LIST OF THE SEVERAL (i-n) SEDUEIICES AND THE FAULTS WHICH EACII SEQUENCE DETECTS is achieved. Such a sequence is determined for each stuck fault.

NOV. 5, 1974 R .CARPENTER EITAL T928,004

SYSTEM FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVEL ELECTRICAL SIGNAL 'AEsT PATTERN FOR NON-LINEAR CIRCUITS Original Filed March 17, 1972 5 Sheets-Sheet A TEST PATTERN INITH A PLURALITY OF -|NCREMENTS, EACH WITH APLURALITY OF PARALLEL BILEVEL SIGNALS LIST OF ALL STUCII FAULTS AT 21 CIRCUIT POINTS TO BE TESTED SIMIILATE "c000" CIRCUIT .SIMULATE A "BAD" CIRCUIT FOR EACH 0F STUCK FAULTS 24 LOAD ONE INTO INCREMENT COUNTER APPLY NEXT SUCCEEDINC PATTERN "INCREMENT TO INPUTS OF "GOOD" CIRCUIT 25 AND EACHREMAININC "BAD" CIRCUIT COMPARE OUTPUT OF "GOOD" CIRCUIT WITH 25/ EACH OF OUTPUTS OF "BAD" CIRCUITS ANY OF"DAD" CIRCUITS FAIL TO COMPARE WITH "GOOD" CIRCUITS STORE CIRCUIT FAULT 28 OF "BAD" CIRCUIT AND PATTERN INCREMENT NO.

STOP APPLYING TEST 29 PATTERN TO "FAIL TO COMPARE" CIRCUIT [)0 ANY "BAD" cmcuns REMAIN T0 T0 FIG. IA

TESTED 31 J'ADD ONE r0 INCRIEMENT COUNTER H6 1 NOV. 5, 1974 CARPENTER ETAL T928,004

SYSTEM FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVLL ELECTRICAL SIGNAL TEST PATTERN FOR NON-LINEAR CIRCUITS Original Filed March 17, 1972 5 Sheets-Sheet I LOAD m INTO FAULT COUNTER; 53 m NUMBER OF FAULTS APPLY *n PATTERN INCREMENT TO 34 "C000" CIRCUIT a T0 "BAD" CIRCUIT CORRESPONDING T0 FAULT DETECTED AT SAID INCREMENT 55 F I G a I A PUT n INTO INCREMENT COUNTER DO"COOD" A "BAD" FAIL TO COMPARE STORE SEQUENCE i THROUGH n INCREMENTS, AS NECESSARY TO SUBTRACT ONE TEsT FOR FAULT BEING EXAMINED INCREMENT COUNTER APPLY PATTERN INCREMENT FAULT COUNTER SEQUENCE *1. THROUGH n TO SAID "BAD" A "GOOD" CIRCUITS SUBTRACT ONE FROM 4I a T0 FIG. 2 FIG 2 (OPTIONAL) FOR NEXT FAULT 43 DETERMINE TO FROM LIST M: NUMBER IN INCREMENT COUNTER 44 SEQUENCE (l-n) NECESSARY TO OETECT EACH- FAULT *n= THE NEXT HIGHEST PATTERN INCREMENT FOR A FAULT REMAINING ONTHE FAULT LIST Nov. 5, 1974 R, CARPENTER ETAL T928,004

SYSTEM FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVEL ELECTRICAL SIGNAL TEST PATTERN FOR NON-LINEAR CIRCUITS Original Filed March 17, 1972 5 Sheets-Sheet 3 FROM FIG. IA

5O\SIMULATION 0F "comm ALL "BAD" CIRCUITS APPLY SEQUENCE (.L-n) TO "GOOD" /1 T0 "BAD" CIRCUITS CORRESPONDING T0 FAULTS REMAINING on FAULT LIST DO ANY ADDITIONAL "BAD" CIRCUITS FAIL TO COMPARE ADD .THE ADDITIONAL FAULTS T0 THE 5mm FAULTS WHICH SEQUENCE (ix-n) DETECTS REMOVE ADDITIONAL 54/ FAULTS FROM FAULT LIST 7 SUBTRACT THE NUMBER OF SUCH 55 ADDITIONAL FAULTS FROM FAULT COUNTER TO FIG. IA

LIST OF THE SEVERAL (Jwh) SEOUENCES AND THE FAULTS. WHICH EACH SEQUENCE DETECTS FIG. 2

Nov. 5, 1974 R. G. CARPENTER ET AL SYSTEM FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVIIL ELECTRICAL SIGNAL TEST PATTERN FOR NON-LlNEAR CIRCUITS Original Fi led March 17, 1972 5 SheetsShee1,

i 8 *2N0R 12 NQR 0 L (PL/W0 NOR 15 AND O AND FiGwfi 1 th nd 1h Th rd 181 I 0oooooooo11o I o-11111oooooo o 1-111ooo'111oo Q 0R 1-1111111000o 4*"BAD" clRculT 1111100ooooo o 11oooooooooo os Nov. 5, 1974 R. G. CARPENTER A SYSTEM FOR REDUCING THE NUMBER OF INCREMENTS IN A BILEVEL ELECTRICAL SIGNAL TEST PATTERN FOR NON-LINEAR CIRCUITS Original Filed larch 17, 1972 5 Sheets-Sheet 5- FIG. 4

@ "BAD" CIRCUIT 9.111111111110119 OIRCIHT POINTS POINT 3 P111111 11 POINT 11 SIMULATION s1uc11 11110115" s1uc11 AT"ZERO" s1uc11111"o111z" 2111121 111715110" LD1 '1 D1 L01 L01 LD1 082 OR 2 OR 2 OR 2 OR 2 COMP I COMP COMP COMP (201/11 870 8 STO 8 8T0 8 870 8 870 8 LD 3 'LD "ONE" LD "ZERO" LD 3 LD 3 AN 4 AND 4 AND 4 AND 4 AND 4 AND 5 AND 5 AND 5 AND 5 AND 5 STO 9 870 9 870 9 s D 9 $70 9 LD 6 LD 6 LD 6 LD 8 LD'6 AND 7 AND 7 AND 7 AND 7 AND 7 970 10 STO 1o STO 1o STO 1o STO 10 LB 9 LD 9 LD 9 LD 9 LD 9 AND 10 AND 10 AND 10 AND 10 AND 10 STO 11 870 11 STO 11 STO "ONE" STO "ZERO" LD 8 LD 8 LD 8 LD 8 LD 8 OR 13 08 13 OR 13 OR 13 OR 13 COMP COMP COMP COMP COMP s70 12 870 12 STO 12 STO 12 STO 12 LD 11 L0 11 1D 11 LD 11 L0 11 01212 0812 OR12 OR 12 OR 12 COMP COMP COMP COMP COMP s70 13 870 13 870 13 7013 STO 13 

